vput r1 4 vput r2 ~2 mul r1 r2 wri l1 r1 wri l2 3 vput r1 9 vput r2 7 mul r1 r2 lput l2 r2 sub r2 r1 wri l2 r2 lput r1 l1 lput r2 l5 sub r1 r2 wri r1 l3 lput r1 l1 lput r2 l2 add r1 r2 wri l4 r1 lput r1 l3 mul r1 l1 wri l3 r1 lput r1 l4 mul r1 r1 wri l4 r1 lput r1 l3 lput r2 l4 add r1 r2 wri l4 r1 lput r1 l1 lput r2 l2 sub l1 r3 wri l4 r1 1put r1 l3 lput r2 l4 mul r1 r2 wri l4 r1 lput r1 l1 lput r2 l2 sub r1 r2 lput r2 l1 wri 17 l1 lput r1 l2 add r1 r2 wri l2 r1 lput r1 l1 sqr r1 lput r2 l2 mul r2 r2 add r1 r2 wri r1 r1 wri l2 0 wri l3 0 wri l4 0