| Date | Topics | Reading |
|---|
| 1/22 | Introduction and overview of computer
architecture | |
| 1/27 | Costs, trends, and performance | 1.1-1.5 |
| 1/29 | Amdahl's law, the CPU performance equation and the memory
hierarchy | 1.6,1.7 |
| 2/3 | Instruction set design | 2.1-2.6 |
| 2/5 | Compilers and DLX | 2.7-2.11 |
| 2/10 | Parallelism and the 5 stage pipeline | 3.1,3.2 |
| 2/12 | Structural hazards | 3.3 |
| 2/17 | Data and control hazards, implementation
issues | 3.4,3.5 |
| 2/19 | Multicycle operations and the MIPS 4000
pipeline | 3.6-3.9 |
| 2/24 | Instruction-level parallelism | 4.1 |
| 2/26 | Dynamic scheduling | 4.2 |
| 3/3 | Branch prediction | 4.3 |
| 3/5 | Superscalar, VLIW, and compiler support | 4.4, 4.5 |
| 3/10 | Hardware support and ILP studies | 4.6, 4.6 |
| 3/12 | PowerPC 620 pipeline | 4.8, 4.9 |
| 3/17 | Spring break | |
| 3/19 | Spring break | |
| 3/24 | Review | |
| 3/26 | Midterm exam | |
| 3/31 | Caches and cache misses | 5.1-5.3 |
| 4/2 | Miss penalty and hit time | 5.4,5.5 |
| 4/7 | Virtual memory | 5.6-5.8 |
| 4/9 | Virtual memory | 5.6-5.8 |
| 4/14 | The Alpha memory hierarchy | 5.9,5.10 |
| 4/16 | Centralized shared-memory systems | 8.1-8.3 |
| 4/21 | Distributed shared-memory systems | 8.4 |
| 4/23 | Synchronization and consistency | 8.5,8.6 |
| 4/28 | The SGI Challenge | 8.7,8.8 |
| 4/30 | Multiprocessor summary | 8.9,8.10 |
| 5/5 | Dataflow and Multithreaded architectures |
Handouts |
| 5/7 | Review | |
| 5/12 | Final Exam | |
| Set | Due date | Exercises |
|---|
| 1 | 2/5 | 1.3, 1.5, 1.6, 1.11, and 1.12 |
| 2 | 2/19 | 2.1, 2.2, 2.3, 2.6, 2.10, and 2.11 |
| 3 | 3/5 | 3.1, 3.3a, 3.3b, 3.6, 3.9, 3.12, and
3.14 |
| 4 | 3/24 | Chapter 4 |
| 5 | 4/28 | Chapter 5 |
| 6 | 5/7 | Chapter 8 |