3 Implementing Control Structures

 

3.1 Goal

To cover the implementation of control structures using the SPARC instruction set.

3.2 Objectives

After completing this lab, you will be able to write assembly language programs that use:

• The condition code register,
• Operations that set the condition code register,
• The conditional and unconditional branching operations of the SPARC, and
• Conditional nullification.

3.3 Discussion

In this lab we introduce a subset of the SPARC branching operations. In particular, we introduce the operations that provide conditional and unconditional branching based on the bits in a condition code register.

We begin by considering the bits in the condition code register of a SPARC processor. After introducing these bits, we consider the operations that affect the bits in the condition code register. We then consider the conditional and unconditional branching operations that use the bits in the condition code register to control branching. Next, we introduce nullification (annulment) in the branching operations of the SPARC. We conclude by considering several examples to illustrate the SPARC operations and by introducing the compare operation provided by the SPARC.

3.3.1 The condition code register

The condition code register on the SPARC has four bits: Z (Zero), N (Negative), C (Carry), and V (oVerflow). The standard arithmetic operations (e.g., addition and subtraction) do not update the bits in the condition code register. Instead, there are special operations that update the condition code register. Table 3.1 summarizes a collection of operations that update the bits in the condition code register. The names for these operations have a suffix of ``cc'' to indicate that they update the bits in the condition code register.

  
Table 3.1: Updating the condition code register

In most cases, the effect that an operation has on the condition codes is just what you would expect. Most of these operations set the Z bit when the result of the operation is zero, and clear this bit when the result is nonzero. Similarly, most of these operations set the N bit when the result of the operation is negative, and clear this bit when the result is nonnegative. The V bit is usually set when the (signed integer) result of the operation cannot be stored in 32 bits, and cleared when the result can be stored in 32 bits. Finally, the C bit is set when the operation generates a carry out of the most significant bit, and cleared otherwise.

In most contexts, you will be most interested in the N and Z bits of the condition code register and we will emphasize these bits in the remainder of this lab. We will consider the remaining bits in the condition code register (the C and V bits) at greater length in Lab 13.

3.3.2 Branching operations

The SPARC provides 16 basic branching operations. These operations are summarized in Table 3.2. Note that the first two operations, ba (branch always) and bn (branch never), are unconditional--the operation specifies whether the branch is taken. The remaining operations are conditional branching operations. When these operations are used, the branch is only taken when the specified condition in met. In last column of Table 3.2 we use a boolean expression involving the bits of the condition code register to specify the condition. The condition is satisfied if the boolean expression results in the value 1; otherwise (if the expression results in 0), the condition is not satisfied and the processor continues with sequential execution of instructions. The target specified in an assembly language instruction is a label defined by the program.

  
Table 3.2: Branching operations on the SPARC

In addition to the operation names defined in Table 10, the SPARC defines several synonyms for these operations. These synonyms are summarized in Table 3.3.

  
Table 3.3: Synonyms for branching operations

Like most RISC machines, the SPARC uses a branch delay slot. By default, the instruction following a branch instruction is executed whenever the branch instruction is executed.

SPARC assemblers provide a special (synthetic) operation, nop, for situations when it is not convenient to put a useful instruction in the delay slot of a branch instruction. In assembly language a nop instruction has no operands (i.e., a nop instruction is fully specified by the name of the operation). When a nop instruction is executed, it does not alter any of the registers or values stored in memory. However, the use of nop instructions causes the processor to execute more instructions and, as such, increases the time required to execute the program. Example 3.1 illustrates the conditional and unconditional branching operations.

Example:   Translate the following C code fragment into SPARC assembly language.

int temp;
int x = 0;
int y = 0x9;
int z = 0x42;

temp = y;
while( temp > 0 ) {
    x = x + z;
    temp = temp - 1;
}

To simplify the translation, we fill the branch delay slots with nop instructions.

        .data
x:      .word   0
y:      .word   0x9
z:      .word   0x42

        .text
start:  set     y, %r1
        ld      [%r1], %r2        ! we'll use %r2 for temp
        set     z, %r1
        ld      [%r1], %r3        ! we'll use %r3 for z
        mov     %r0, %r4          ! we'll use %r4 for x

        add     %r2, 1, %r2       ! set up for decrement
        ba      test              ! test the loop condition
        nop                       ! BRANCH DELAY SLOT
top:    add     %r4, %r3, %r4     ! x + z --> x
test:   subcc   %r2, 1, %r2       ! temp - 1 --> temp
        bg      top               ! temp > 0 ?
        nop                       ! BRANCH DELAY SLOT

        set     x, %r1
        st      %r4, [%r1]        ! store x
end:    ta      0

Activity:   After each trace command, ISEM reports the values of the bit in the condition code register. Type the program shown Example 3.1 into a file, assemble it, link it, and load it into ISEM. Trace the program execution, noting how each instruction affects the bits in the SPARC condition code register.

The SPARC keeps track of the instructions to execute using two program counters: PC, and nPC. The first program counter, PC, holds the address of the next instruction to execute. The second program counter, nPC, holds the next value for PC. Usually, the SPARC updates the program counters at the end of each instruction execution by assigning the current value of nPC to PC, and adding 4 to the value of nPC. When it executes a branching operation, the SPARC assigns the current value of nPC to PC and then updates the value of nPC. If the branch is taken, nPC is assigned the value of the target specified in the instruction; otherwise, nPC is incremented by 4. The branch delay slot arises because the PC is assigned the old value of nPC (before nPC is assigned the target of the branch).

Activity: After each trace command, ISEM reports the values of PC and nPC. Run the program shown in Example 3.1 noting the changes to PC and nPC.

3.3.3 Nullification

Every branching instruction can specify that the affect of the instruction in the branch delay slot is to be nullified (annulled in SPARC terminology) if the branch specified by the conditional branching instruction is not taken. In assembly language, this conditional nullification is specified by appending a suffix of ``,a'' to the name of the branching operation. Example 3.2 illustrates conditional nullification.

Example:   Rewrite the code fragment shown in Example 3.1 so that the code has meaningful instructions in the branch delay slots.

        .data
x:      .word   0
y:      .word   0x9
z:      .word   0x42

        .text
start:  set     y, %r1
        ld      [%r1], %r2        ! we'll use %r2 for temp
        set     z, %r1
        ld      [%r1], %r3        ! we'll use %r3 for z
        mov     %r0, %r4          ! we'll use %r4 for x

        add     %r2, 1, %r2       ! set up for decrement
top:    subcc   %r2, 1, %r2       ! temp - 1 --> temp
        bg,a    top               ! temp > 0 ?
        add     %r4, %r3, %r4     ! x + z --> x

        set     x, %r1
        st      %r4, [%r1]        ! store x
end:    ta      0

3.3.4 The (synthetic) integer comparison operation

Assemblers for the SPARC provide a synthetic integer comparison operation. You can use this operation when the data manipulation operations do not establish the needed values in the condition code register. Table 3.4 summarizes the integer comparison operation. This operation can be used to compare the contents of two registers or to compare the contents of a register with a small integer constant.

  
Table 3.4: Signed integer comparison

3.3.5 Delayed control-transfer couples

When a branch instruction is in the delay slot of another branch instruction, the pair of branch instructions is called a ``delayed control-transfer couple''. If you use a delayed control-transfer couple on the SPARC, the first branch operation should be an unconditional branch; otherwise, the sequence of instructions executed when the delayed control-transfer couple is executed is not defined. We will consider delayed control-transfer couples in greater depth when we consider traps and exceptions in Lab 16.

3.4 Summary

In this lab we have introduced the condition code register, the basic branching operations, and the integer comparison operation. The branching operations include two unconditional branch operations ( ba and bn) and a host of conditional branching operations. The SPARC branching operations have a branch delay slot. That is, the instruction following a branch instruction is executed whenever the branch instruction is executed. The SPARC provides conditional annulment of the instruction in the branch delay slot. When the branch operation specifies annulment (using the operator suffix ``,a''), the affects of the instruction are canceled (note, the instruction is executed, but the execution has no affect).

3.5 Review Questions

1. What are the bits in the condition code register.
2. Name two operations that affect the bits in the condition code register and explain how they affect these bits.
3. What are the two program counters on the SPARC. Explain how these program counters are used.
4. Is the affect of the instruction in the delay slot of an annulled branch canceled when the branch is take or when the branch is not taken? Explain why the designers of the SPARC chose the this version of nullification.

3.6 Exercises

1. Suppose that your assembler did not provide an integer comparison operation. Explain how you could implement this operation using the other SPARC operations that we have considered in this and previous labs.
2. Consider the SPARC code presented in Example 3.2. Currently, the loop is executed ``y'' times. If ``y'' is larger than ``z'' it would be better to execute the loop ``z'' times. Rewrite the code shown in Example 3.2 to take advantage of this observation.
3. Write a SPARC program that has four variables: , y > 0, z, and w. Your program should assign the quotient of x/y to z and the remainder to w. (You should write this code using the operations presented in this and previous labs. Do not use the SPARC integer multiplication or division operations.
4. Write a SPARC program that will compute the greatest common divisor of a and b and assign this value to c.